- Add Master output audio ports
- Update .gitignore
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parent
f405ce33ad
commit
2debad5744
10
.gitignore
vendored
10
.gitignore
vendored
@ -1,7 +1,9 @@
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drmr.so
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*~
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drmr_ui.xml
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drmr2.so
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drmr_ui.so
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drmr2_ui.xml
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drmr.lv2
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drmr2_ui.so
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drmr2.lv2
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drmr2.ttl
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build
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build
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/logo.xcf
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/logo.xcf
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/htest
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/htest
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14
drmr2-mkttl
14
drmr2-mkttl
@ -70,7 +70,19 @@ add_port "," " a lv2:InputPort , atom:AtomPort;
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lv2:name \"Control\";"
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lv2:name \"Control\";"
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idx=1
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add_port "," " a lv2:AudioPort, lv2:OutputPort;
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lv2:index %d;
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lv2:symbol \"master_out_1\";
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lv2:name \"Master - Out 1\";"
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add_port "," " a lv2:AudioPort, lv2:OutputPort;
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lv2:index %d;
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lv2:symbol \"master_out_2\";
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lv2:name \"Master - Out 2\";"
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out_id=0
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out_id=0
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while [[ "${out_id}" -lt "${outport_nb}" ]]
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while [[ "${out_id}" -lt "${outport_nb}" ]]
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26
drmr2.c
26
drmr2.c
@ -166,7 +166,15 @@ connect_port(LV2_Handle instance,
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break;
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break;
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default:
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default:
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if( port_index >= DRMR_LEFT_00 && port_index <= DRMR_RIGHT_31)
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if( port_index == DRMR_MASTER_LEFT)
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{
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drmr->master_right = (float*)data;
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}
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else if( port_index == DRMR_MASTER_RIGHT)
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{
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drmr->master_left = (float*)data;
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}
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else if( port_index >= DRMR_LEFT_00 && port_index <= DRMR_RIGHT_31)
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{
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{
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int outoff = (port_index - DRMR_LEFT_00) / 2;
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int outoff = (port_index - DRMR_LEFT_00) / 2;
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@ -357,7 +365,8 @@ static void run(LV2_Handle instance, uint32_t n_samples) {
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{
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{
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case 8:
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case 8:
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{
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{
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if (!drmr->ignore_note_off) {
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if (!drmr->ignore_note_off)
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{
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nn = data[1];
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nn = data[1];
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nn-=baseNote;
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nn-=baseNote;
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untrigger_sample(drmr,nn,offset);
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untrigger_sample(drmr,nn,offset);
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@ -450,6 +459,12 @@ static void run(LV2_Handle instance, uint32_t n_samples) {
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pthread_mutex_lock(&drmr->load_mutex);
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pthread_mutex_lock(&drmr->load_mutex);
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for( j = 0; j<n_samples; j++)
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{
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drmr->master_left[j] = 0.0f;
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drmr->master_right[j] = 0.0f;
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}
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for (i = 0;i < drmr->num_samples;i++)
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for (i = 0;i < drmr->num_samples;i++)
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{
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{
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int pos,lim;
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int pos,lim;
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@ -496,8 +511,12 @@ static void run(LV2_Handle instance, uint32_t n_samples) {
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for (pos = datastart; pos < lim && pos < dataend; pos++)
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for (pos = datastart; pos < lim && pos < dataend; pos++)
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{
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{
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drmr->master_left[pos] += cs->data[cs->offset]*coef_left;
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drmr->left[i][pos] += cs->data[cs->offset]*coef_left;
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drmr->left[i][pos] += cs->data[cs->offset]*coef_left;
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drmr->master_right[pos] += cs->data[cs->offset]*coef_right;
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drmr->right[i][pos] += cs->data[cs->offset]*coef_right;
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drmr->right[i][pos] += cs->data[cs->offset]*coef_right;
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cs->offset++;
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cs->offset++;
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}
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}
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}
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}
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@ -508,7 +527,10 @@ static void run(LV2_Handle instance, uint32_t n_samples) {
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if (lim > n_samples) lim = n_samples;
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if (lim > n_samples) lim = n_samples;
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for (pos = datastart; pos < lim && pos < dataend; pos++)
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for (pos = datastart; pos < lim && pos < dataend; pos++)
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{
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{
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drmr->master_left[pos] += cs->data[cs->offset]*coef_left;
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drmr->left[i][pos] += cs->data[cs->offset++]*coef_left;
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drmr->left[i][pos] += cs->data[cs->offset++]*coef_left;
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drmr->master_right[pos] += cs->data[cs->offset]*coef_right;
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drmr->right[i][pos] += cs->data[cs->offset++]*coef_right;
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drmr->right[i][pos] += cs->data[cs->offset++]*coef_right;
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}
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}
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}
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}
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4
drmr2.h
4
drmr2.h
@ -72,6 +72,8 @@ typedef struct {
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typedef enum {
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typedef enum {
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DRMR_CONTROL = 0,
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DRMR_CONTROL = 0,
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DRMR_MASTER_LEFT,
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DRMR_MASTER_RIGHT,
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DRMR_LEFT_00,
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DRMR_LEFT_00,
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DRMR_RIGHT_00,
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DRMR_RIGHT_00,
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DRMR_LEFT_01,
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DRMR_LEFT_01,
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@ -225,6 +227,8 @@ typedef struct {
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typedef struct {
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typedef struct {
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// Ports
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// Ports
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float* master_left;
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float* master_right;
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float** left;
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float** left;
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float** right;
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float** right;
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LV2_Atom_Sequence *control_port;
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LV2_Atom_Sequence *control_port;
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